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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos, high speed 1-, 4- & 8-channel 10-bit adcs ad7776/ad7777/ad7778* functional block diagrams cs rd wr busy/int agnd db0?b9 ad7776 10 dgnd clkin 10 control register adcreg1 t/h refout refin ref agnd c refin rtn v swing v bias a in 1 mux refin 10-bit adc control logic v cc agnd db0?b9 ad7777 10 control register dgnd clkin 10 adcreg2 adcreg1 t/h 1 refout refin ref agnd c refin v swing v bias a in 1 a in 2 a in 3 a in 4 mux 1 refin t/h 2 mux 2 10-bit adc control logic v cc rtn agnd db0?b9 ad7778 10 control register dgnd clkin cs rd wr busy/int 10 adcreg2 adcreg1 t/h 1 refout refin ref agnd c refin v swing v bias a in 1 a in 2 a in 3 a in 4 a in 5 a in 6 a in 7 a in 8 mux 1 refin t/h 2 mux 2 10-bit adc control logic v cc rtn features ad7776: single channel ad7777: 4-channel ad7778: 8-channel fast 10-bit adc: 2.5 m s worst case +5 v only half-scale conversion option fast interface port power-down mode applications hdd servos instrumentation general description the ad7776, ad7777 and ad7778 are a family of high speed, multichannel, 10-bit adcs primarily intended for use in r/w head positioning servos found in high density hard disk drives. they have unique input signal conditioning features that make them ideal for use in such single supply applications. by setting a bit in a control register within both the four-channel version, ad7777, and the eight-channel version, ad7778, the input channels can either be independently sampled or any two channels of choice can be simultaneously sampled. for all ver- sions the specified input signal range is of the form v bias v swing . however, if the rtn pin is biased at, say, 2 v the analog i nput signal range becomes 0 v to +2 v for all input channels. this is covered in more detail under the section changing the analog input voltage range. the voltage v bias is the offset of the adcs midpoint code from ground and is supplied either by an onboard reference available to the user (refout) or by an external voltage reference applied to refin. the full-scale range (fsr) of the adc is equal to 2 v swing where v swing is nominally equal to refin/2. addi- tionally, when placed in the half-scale conversion mode, the value of refin is converted. this allows the channel offset(s) to be measured. control register loading and adc register reading, channel se- lect and conversion start are under the control of the m p. the twos complemented coded adcs are easily interfaced to a stan- dard 16-bit mpu bus via their 10-bit data port and standard microprocessor control lines. the ad7776/ad7777/ad7778 are fabricated in linear compat- ible cmos (lc 2 mos), an advanced, mixed technology process that combines precision bipolar circuits with low power cmos logic. the ad7776 is available in a 24-pin soic package; the ad7777 is available in both 28-pin dip and 28-pin soic pack- ages; the ad7778 is available in a 44-pin pqfp package. * protected by u.s. patent no. 4,990,916. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997
rev. 0 C2C ad7776/ad7777/ad7778Cspecifications (v cc = +5 v 6 5%; agnd = dgnd = o v; clkin = 8 mhz; rtn = o v; c refin = 10 nf; all specifications t min to t max unless otherwise noted.) parameter a versions 1 units conditions/comments dc accuracy resolution 2 10 bits relative accuracy 1 lsb max see terminology differential nonlinearity 1 lsb max no missing codes; see terminology bias offset error 12 lsb max see terminology bias offset error match 10 lsb max between channels, ad7777/ad7778 only; see terminology plus or minus full-scale error 12 lsb max see terminology plus or minus full-scale error match 10 lsb max between channels, ad7777/ad7778 only; see terminology analog inputs input voltage range all inputs v bias v swing v min/v max input current +200 m a max v in = v bias v swing ; any channel reference input refin 1.9/2.1 v min/v max for specified performance refin input current +200 m a max reference output refout 1.9/2.1 v min/v max nominal refout = 2.0 v dc output impedance 5 w typ reference load change 2 mv max for reference load current change of 0 to 500 m a 5 mv max for reference load current change of 0 to 1 ma reference load should not change during conversion short circuit current 3 20 ma max see terminology logic outputs db0Cdb9, busy / int v ol , output low voltage 0.4 v max i sink = 1.6 ma v oh , output high voltage 4.0 v min i source = 200 m a floating state leakage current 10 m a max floating state capacitance 3 10 pf max adc output coding twos complement logic inputs db0Cdb9, cs , wr , rd , clkin input low voltage, v inl 0.8 v max input high voltage, v inh 2.4 v min input leakage current 10 m a max input capacitance 3 10 pf max conversion timing acquisition time 4.5 t clkin ns min see terminology 5.5 t clkin + 70 ns max single conversion 14 t clkin ns max double conversion 28 t clkin ns max t clkin 125/500 ns min/ns max period of input clock clkin t clkin high 50 ns min minimum high time for clkin t clkin low 40 ns min minimum low time for clkin power requirements v cc range +4.75/+5.25 v min/v max for specified performance i cc , normal mode 15 ma max cs = rd = +5 v, cr8 = 0 i cc , power-down mode 1.5 ma max cr8 = 1. all linear circuitry off power-up time to operational specifications 500 m s max from power-down mode dynamic performance see terminology signal to noise and distortion s/(n+d) ratio C57 db min v in = 99.88 khz full-scale sine wave with f sampling = 380.95 khz total harmonic distortion (thd) C60 db min v in = 99.88 khz full-scale sine wave with f sampling = 380.95 khz intermodulation distortion (imd) C75 db typ fa = 103.2 khz, fb = 96.5 khz with f sampling = 380.95 khz. both signals are sine waves at half-scale amplitude channel-to-channel isolation C90 db typ v in = 100 khz full-scale sine wave with f sampling = 380.95 khz notes 1 temperature range as follows: a = C40 c to +85 c. 2 1 lsb = (2 v swing )/1024 = 1.95 mv for v swing = 1.0 v. 3 guaranteed by design, not production tested. specifications subject to change without notice.
ad7776/ad7777/ad7778 C3C rev. 0 timing specifications 1, 2 (v cc = +5 v 6 5%; agnd = dgnd = 0 v; all specifications t min to t max unless otherwise noted.) t 3 t 11 t 10 t 9 t 8 first conversion finished (cr6 = 0) second conversion finished (cr6 = 1) ad7777/ad7778 only t 9 busy (cr8 = 0) int (cr8 = 1) t 10 wr, rd figure 3. busy / int timing i ol 1.6ma +2.1v i oh 200 m a c out 100pf db n figure 4. load circuit for bus timing characteristics t 1 cs t 2 t 4 t 5 rd db0?b9 figure 1. read cycle timing t 1 cs t 2 t 6 wr db0?b9 t 3 t 7 figure 2. write cycle timing parameter label limit at t min to t max units test conditions/comments interface timing cs falling edge to wr or rd falling edge t 1 0 ns min wr or rd rising edge to cs rising edge t 2 0 ns min wr pulse width t 3 53 ns min cs or rd active to valid data 3 t 4 60 ns max timed from whichever occurs last bus relinquish time after rd 4 t 5 10 ns min 45 ns max data valid to wr rising edge t 6 55 ns min data valid after wr rising edge t 7 10 ns min wr rising edge to busy falling edge t 8 1.5 t clkin ns min cr9 = 0 2.5 t clkin + 70 ns max wr rising edge to busy rising edge or int falling edge t 9 19.5 t clkin + 70 ns max single conversion, cr6 = 0 t 10 33.5 t clkin + 70 ns max double conversion, cr6 = 1 wr or rd falling edge to int rising edge t 11 60 ns max cr9 = 1 notes 1 see figures 1 to 3. 2 timing specifications in bold print are 100% production tested. all other times are guaranteed by design, not production tested. all input signals are speci fied with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 3 t 4 is measured with the load circuit of figure 4 and defined as the time required for an output to cross 0.8 v or 2.4 v. 4 t 5 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 4. the meas ured time is then extrapolated back to remove the effects of charging or discharging the 100 pf capacitor. this means that the time t 5 quoted above is the true bus relinquish time of the device and, as such, is independent of the external bus loading capacitance. specifications subject to change without notice.
ad7776/ad7777/ad7778 C4C rev. 0 absolute maximum ratings* (t a = +25 c unless otherwise noted) v cc to agnd or dgnd . . . . . . . . . . . . . . . . . . C0.3 v, +7 v agnd, rtn to dgnd . . . . . . . . . . . . . C0.3 v, v cc + 0.3 v cs , rd , wr , clkin, db0Cdb9, busy / int to dgnd . . . . . . . . . . . . . C0.3 v, v cc + 0.3 v analog input voltage to agnd . . . . . . . C0.3 v, v cc + 0.3 v refout to agnd . . . . . . . . . . . . . . . . C0.3 v, v cc + 0.3 v refin to agnd . . . . . . . . . . . . . . . . . . C0.3 v, v cc + 0.3 v operating temperature range all versions . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c dip package, power dissipation . . . . . . . . . . . . . . . . 875 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering (10 sec) . . . . . . . . . . +260 c soic packages, power dissipation . . . . . . . . . . . . . . 875 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c pqfp package, power dissipation . . . . . . . . . . . . . . 500 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 95 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configurations warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7776/ad7777/ad7778 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 24-pin soic 1 2 24 23 22 10 15 11 12 14 13 21 20 18 17 16 19 9 3 4 5 top view (not to scale) 7 8 6 ad7776 db2 db3 dgnd db4 db5 db6 db7 db1 db0 c refin agnd rtn refin a in agnd refout v cc db8 (msb) db9 clkin busy/int rd wr cs 28-pin dip & soic 1 2 24 23 22 10 15 11 12 14 13 21 20 17 16 9 3 4 5 7 8 6 18 19 top view (not to scale) 28 27 26 25 ad7777 nc nc = no connect db2 db3 dgnd db4 db5 db6 db7 db1 db0 db8 (msb) db9 busy/int c refin agnd rtn refin agnd refout v cc clkin rd wr cs a in 4 a in 3 a in 2 a in 1 ordering guide temperature no. of package model range channels option 1 ad7776ar 2 C40 c to +85 c 1 r-24 ad7777an C40 c to +85 c 4 n-28 ad7777ar 2 C40 c to +85 c 4 r-28 ad7778as 2 C40 c to +85 c 8 s-44 notes 1 r = soic, n = plastic dip, s = pqfp. 2 analog devices reserves the right to ship devices branded with a j in place of the a, e.g., ad7776jr instead of ad7776ar. temperature range remains C40 c to +85 c. 44-pin pqfp 7 8 9 10 11 6 5 4 3 2 1 33 32 31 30 29 28 27 26 25 24 23 18 19 20 21 22 17 16 15 14 13 12 39 38 37 36 35 34 44 43 42 41 40 top view (not to scale) ad7778 nc nc nc nc nc nc nc nc nc nc nc nc nc db2 db3 dgnd db4 db5 db6 db7 db1 db0 c refin rtn agnd refin a in 8 a in 7 a in 6 a in 5 a in 4 a in 3 a in 2 a in 1 agnd refout v cc db8 (msb) db9 clkin busy/int rd wr cs nc = no connect
ad7776/ad7777/ad7778 C5C rev. 0 pin function description mnemonic description v cc +5 v power supply. agnd analog ground. dgnd digital ground. ground reference for digital circuitry. db0Cdb9 input/output data bus. this is a bidirectional data port from which adc output data may be read and to which control register data may be written. busy / int busy/interrupt output. active low logic output indicating a/d converter status. this logic output has two modes of operation depending on whether location cr9 of the control register has been set low or high: if cr9 is set low, then the busy / int output will behave as a busy signal. the busy signal will go low and stay low for the duration of a single conversion, or if simultaneous sampling has been selected, busy will stay low for the duration of both conversions. if cr9 is set high, then the busy / int output behaves as an interrupt signal. the int signal will go low and remain low after either a single conversion is completed or after a double conversion is completed if simulta- neous sampling has been selected. with cr9 high, the falling edge of wr or rd resets the int line high. cs chip select input. the device is selected when this input is low. wr write input (active low). it is used in conjunction with cs to write data to the control register. data is latched to the registers on the rising edge of wr . following the rising edge of wr , the analog input is acquired and a conversion is started. rd read input (active low). it is used in conjunction with cs to enable the data outputs from the adc registers. a in 1C8 analog inputs 1C8. the analog input range is v bias v swing where v bias and v swing are defined by the reference voltage applied to refin. input resistance between any of the analog input pins and agnd is 10 k w or greater. refin voltage reference input. the ad7776/ad7777/ad7778 are specified over a voltage reference range of 1.9 v to 2.1 v with a nominal value of 2.0 v. this refin voltage provides the v bias and v swing levels for the input channel(s). v bias is equal to refin and v swing is nominally equal to refin/2. input resistance between this refin pin and agnd is 10 k w or greater. refout voltage reference output. the internal voltage reference, which is nominally 2.0 v and can be used to provide the bias voltage (v bias ) for the input channel(s), is provided at this pin. c refin reference decoupling capacitor. a 10 nf capacitor must be connected from this pin to agnd to ensure correct operation of the high speed adc. rtn signal return path for the input channel(s). normally rtn is connected to agnd at the package. circuit description adc transfer function for all versions, an input signal of the form v bias v swing is expected. this v bias signal level operates as a pseudo ground to which all input signals must be referred. the v bias level is de- termined by the voltage applied to the refin pin. this can be driven by an external voltage source or, alternatively, the on- board 2 v reference, available at refout, can be used. the magnitude of the input signal swing is equal to v bias /2 (or refin/2) and is set internally. with a refin of 2 v, the analog input signal level varies from 1 v up to 3 v i.e., 2 1 v. fig- ure 5 shows the transfer function of the adc and its relation- ship to v bias and v swing . the half-scale twos complement code of the adc, 000 hex (00 0000 0000 binary), occurs at an input voltage equal to v bias . the input full-scale range of the adc is equal to 2 v swing , so that the plus full-scale transition (1fe to 1ff) occurs at a voltage equal to v bias + v swing C 1.5 lsbs and the minus full-scale code transition (200 to 201) occurs at a voltage v bias C v swing + 0.5 lsbs. adc output code (hex) 1ff 1fe 202 201 200 000 v bias ? swing v bias v bias +v swing analog input, v in figure 5. adc transfer function
ad7776/ad7777/ad7778 C6C rev. 0 cr6: determines whether operation is on a single channel or simultaneous sampling on two channels. location cr6 is a dont care for the ad7776. cr6 function 0 single channel operation. channel select address is contained in locations cr0Ccr2. 1 two channels simultaneously sampled and sequentially converted. channel select addresses contained in locations cr0Ccr2 and cr3Ccr5. cr7: determines whether the device is in the normal operating mode or in the half-scale test mode. cr7 function 0 normal operating mode 1 half-scale test mode in the half-scale test mode refin is internally connected as an analog input(s). in this mode locations cr0Ccr2 and cr3C cr5 are all dont cares since it is refin which will be con- verted. for the ad7777 and ad7778, the contents of location cr6 still determine whether a single or a double conversion is carried out on the refin level. cr8: determines whether the device is in the normal operating mode or in the powerdown mode. cr8 function 0 normal operating mode 1 powerdown mode in the powerdown mode all linear circuitry is turned off and the refout output is weakly (5 k w ) pulled to agnd. the input impedance of the analog inputs and of the refin input re- mains the same in either normal mode or powerdown mode. see under circuit descriptionpowerdown mode. cr9: determines whether busy / int output flag goes low and remains low during conversion(s) or else goes low and remains low after the conversion(s) is (are) complete. cr9 busy/ int functionality 0 output goes low and remains low during conversion(s). 1 output goes low and remains low after conversion(s) is (are) complete. adc conversion start timing figure 6 shows the operating waveforms for the start of a con- version cycle. on the rising edge of wr , the conversion cycle starts with the acquisition and tracking of the selected adc channel, a in 1C8. the analog input voltage is held 40 ns (typi- cally) after the first rising edge of clkin following four com- plete clkin cycles. if t d in figure 6 is greater than 12 ns, the falling edge of clkin as shown will be seen as the first falling clock edge. if t d is less than 12 ns, the first falling clock edge to be recognized will not occur until one cycle later. following the hold on the analog input(s), two complete clkin cycles are allowed for settling purposes before the msb decision is made. the actual decision point occurs approximately 40 ns after the rising edge of clkin as shown in figure 6. a further two clkin cycles are allowed for the second msb decision. the succeeding bit decisions are made approximately 40 ns after each rising edge of clkin until the conversion is compl ete. at the end of conversion, if a single conversion has been requested (cr6 = 0), the busy / int line changes control register the control register is 10-bits wide and can only be written to. on power-on, all locations in the control register are automati- cally loaded with 0s. for the single channel ad7776, locations cr0 to cr6 of the control register are dont cares. for the quad channel ad7777, locations cr2 and cr5 are dont cares. individual bit functions are described below. cr0Ccr2: channel address locations. determines which channel will be selected and converted for single channel operation. for si- multaneous sampling operation cr0Ccr2 holds the address of one of the two channels to be sampled. ad7776 cr2 cr1 cr0 function x* x x select a in 1 *x = dont care ad7777 cr2 cr1 cr0 function x* 0 0 select a in 1 x 0 1 select a in 2 x 1 0 select a in 3 x 1 1 select a in 4 *x = dont care ad7778 cr2 cr1 cr0 function 0 0 0 select a in 1 0 0 1 select a in 2 0 1 0 select a in 3 0 1 1 select a in 4 1 0 0 select a in 5 1 0 1 select a in 6 1 1 0 select a in 7 1 1 1 select a in 8 cr3Ccr5: channel address locations. only applicable for simul- taneous sampling with the ad7777 or ad7778 when cr3Ccr5 holds the address of the second channel to be sampled. ad7777 cr5 cr4 cr3 function x* 0 0 select a in 1 x 0 1 select a in 2 x 1 0 select a in 3 x 1 1 select a in 4 *x = dont care ad7778 cr5 cr4 cr3 function 0 0 0 select a in 1 0 0 1 select a in 2 0 1 0 select a in 3 0 1 1 select a in 4 1 0 0 select a in 5 1 0 1 select a in 6 1 1 0 select a in 7 1 1 1 select a in 8
ad7776/ad7777/ad7778 C7C rev. 0 state (as programmed by cr9), and the sar contents are trans- ferred to the first register adcreg1. the sar is then reset in readiness for a new conversion. if simultaneous sampling has been requested (cr6 = 1), no change occurs in the status of the busy / int output and the adc automatically starts the second conversion. at the end of this conversion the busy / int line changes state (as programmed by cr9) and the sar contents are transferred to the second register, adcreg2. t d * clkin v in wr channel acquisition 40ns typ 40ns typ 'hold' db9 (msb) * timing shown for t d greater than 12ns figure 6. adc conversion start timing track-and-hold the track-and-hold (t/h) amplifiers on the analog input(s) of the ad7776/ad7777/ad7778 allow the adc to accurately convert an input sine wave of 2 v peak-peak amplitude up to a frequency of 189 khz, the nyquist frequency of the adc when operated at its maximum throughput rate of 378 khz. this maximum rate of conversion includes conversion time and time between conversions. because the input bandwidth of the track- and-hold is much greater than 189 khz, the input signal should be band limited to avoid folding unwanted signals into the band of interest. powerdown the ad7776/ad7777/ad7778 can be placed in a powerdown mode simply by writing a logic high to location cr8 of the con- trol register. the following changes are effected immediately on writing a 1 to location cr8: ? any conversion in progress is terminated. ? if a conversion is in progress, the leading edge of wr immedi- ately drives the busy / int output high. ? all the linear circuitry is turned off. ? the refout output stops being driven and is weakly (5 k w ) pulled to analog ground. control inputs cs , wr and rd retain their purpose while the ad7776/ ad7777/ad7778 is in powerdown. if no conversions are in progress when the ad7776/ad7777/ad7778 is placed into the powerdown modes, the contents of the adc registers, adcreg1 and adcreg2, are retained during powerdown and can be read as normal. on returning to normal operating mode a new conversion (or conversions, dependent on cr6) is automatically started. on completion, the invalid conversion results are loaded into the adc registers losing the previous valid results. in order to achieve the lowest possible power consumption in the powerdown mode special attention must be paid to the state of the digital and analog inputs and outputs: ? because each analog input channel sees a resistive divider to agnd, the input resistance of which does not change be- tween normal and powerdown modes, driving the analog input signals to 0 v or as close as possible to 0 v will minimize the power dissipated in the input signal conditioning circuitry. ? similarly, the refin input sees a resistive divider to agnd, the input resistance of which does not change between normal and powerdown modes. if an external reference is being used, then driving this reference input to 0 v or as close as possible to 0 v will minimize the power dissipated in the input signal conditioning circuitry. ? since the refout pin is pulled to agnd via, typically, a 5 k w resistor, any voltage above 0 v that this output may be pulled to by external circuitry will dissipate unnecessary power. ? digital inputs cs , wr & rd should all be held at v cc or as close as possible. clkin should be held as close as possible to either 0 v or v cc. ? since the busy / int output is actively driven to a logic high, any loading on this pin to 0 v will dissipate power. the ad7776/ad7777/ad7778 comes out of the powerdown mode when a logic 0 is written to location cr8 of the con- trol register. note that the contents of the other locations in the control register are retained when the device is placed in powerdown and are valid when power is restored. however, coming out of powerdown provides an opportunity to reload the complete contents of the control reg ister without any extra instructions.
ad7776/ad7777/ad7778 C8C rev. 0 microprocessor interfacing circuits the ad7776/ad7777/ad7778 family of adcs is intended to interface to dsp machines such as the adsp-2101, adsp-2105, the tms320 family and microcontrollers such as the 80c196 family. figure 7 shows the ad7776/ad7777/ad7778 interfaced to the tms320c10 @ 20.5 mhz and the tms320c14 @ 25 mhz. figure 8 shows the interface with the tms320c25 @ 40 mhz. note that one wait state is required with this interface. the adsp-2101-50 and the adsp-2105-40 interface is shown in figure 9. one wait state is required with either of these machines. * additional pins omitted for clarity addr decode address bus data bus d15?0 tms320c10-20.5 tms320c14-25 a11?0 we (c10) den (c14) ren cs db9?b0 ad7776/7/8* rd wr figure 7. ad7776/ad7777/ad7778 to tms320c10 and tms320c14 interface address bus data bus * additional pins omitted for clarity cs db9?b0 ad7776/7/8* rd wr addr decode d15?0 a15?0 is ready msc strb r/w tms320c25-40 figure 8. ad 7776/ad7777/ad7778 to tms320c25 in terface figure 10 shows the interface with the 80c196kb @ 12 mhz and the 80c196kc @ 16 mhz. one wait state is required with the 16 mhz machine. the 80c196 is configured to operate with a 16-bit multiplexed address/data bus. table i gives a truth table for the ad7776/ad7777/ad7778 and summarizes their microprocessor interfacing features. note that a read instruction to any of the devices while a conversation is in progress will immediately stop that conversion and return unreliable data over the data bus. * additional pins omitted for clarity address bus data bus cs db9?b0 ad7776/7/8* rd wr d23?6 a13?0 wr rd dms adsp-2101-50 adsp-2105-40 addr decode en figure 9. ad7776/ad7777/ad7778 to adsp-2101 and adsp-2105 interface * additional pins omitted for clarity data bus (10) cs db9?b0 ad7776/7/8* rd wr addr decoder '373 latch address bus ad7?d0 (port 3) ad15?d6 (port 4) wr rd 80c196kb-12 80c196kc-16 ale figure 10. ad7776/ad7777/ad7778 to 80c196 interface
ad7776/ad7777/ad7778 C9C rev. 0 table i. ad7776/ad7777/ad7778 truth table for microprocessor interfacing cs rd wr db0Cdb9 function/comments 1 x* x* high z data port high impedance 01 j cr data load control register (cr) data to control register and start a conversion. 0 k 1 adc data adc data placed on data bus. depending upon location cr6 of the control register, one or two read instructions will be required. if cr6 is low, i.e., single channel conversion selected, a read instruction returns the contents of adcreg1. succeeding read instructions continue to return the contents of adcreg1. if cr6 is high, i.e., simultaneous sampling (double conversion) selected, the first read instruction returns the contents of adcreg1 while the second read instruction returns the contents of adcreg2. a third read instruction returns adcreg1 again, the fourth adcreg2, etc. *x = dont care design information layout hints ensure that the layout for the printed circuit board has the digi- tal and analog grounds separated as much as possible. take care not to run any digital track alongside an analog signal track. guard (screen) the analog input(s) with rtn. establish a single point analog ground separate from the logic system ground and as close as possible to the ad7776/ad7777/ ad7778. both the rtn and agnd pins on the ad7776/ ad7777/ad7778 and all other signal grounds should be con- nected to this single point analog ground. in turn, this star ground should be connected to the digital ground at one point onlypreferably at the low impedance power supply itself. low impedance analog and digital power supply common re- turns are important for correct operation of the devices, so make the foil width for these tracks as wide as possible. in order to ensure a low impedance +5 v power supply at the actual v cc pin, it will be necessary to employ bypass capacitors from the pin itself to dgnd. a 4.7 m f tantalum capacitor in parallel with a 0.1 m f ceramic capacitor is sufficient. adc corruption executing a read instruction to the ad7776/ad7777/ad7778 while a conversion is in progress will immediately halt the con- version and return invalid data over the data bus. the busy / int output pin should be monitored closely and all read in- structions to the ad7776/ad7777/ad7778 prevented while this output shows that a conversion is in progress. executing a write instruction to the ad7776/ad7777/ad7778 while a conversion is in progress immediately halts the conver- sion, the falling edge of wr driving the busy / int output high. the analog input(s) is sampled as normal and a new conversion sequence (dependent upon cr6) is started. adc conversion time although each conversion takes only 14 clkin cycles, it can take between 4.5 to 5.5 clkin cycles to acquire the analog input(s) after the wr input goes high and before any conver- sions start. terminology relative accuracy for the ad7776, ad7777 and ad7778, relative accuracy or endpoint nonlinearity is the maximum deviation, in lsbs, of the adcs actual code transition points from a straight line drawn between the endpoints of the adc transfer function. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified maximum differential nonlinearity of 1 lsb ensures no missed codes. bias offset error for an ideal 10-bit adc, the output code for an input voltage equal to v bias should be midscale. the bias offset error is the difference between the actual midpoint voltage for midscale code and v bias , expressed in lsbs. bias offset error match this is a measure of how closely the bias offset errors of all channels track each other. the bias offset error match of any channel must be no further away than 10 lsbs from the bias offset error of any other channel, regardless of whether the channels are independently sampled or simultaneously sampled. plus and minus full-scale error the input channels of the adc can be considered to have bipolar (positive and negative) input ranges, but which are re- ferred to v bias (or refin) instead of agnd. positive full-scale error for the adc is the difference between the actual input voltage required to produce the plus full-scale code transition and the ideal input voltage (v bias + v swing C1.5 lsb), ex- pressed in lsbs. minus full-scale error is similarly specified for the minus full-scale code transition, relative to the ideal input voltage for this transition (v bias C v swing + 0.5 lsb). note that the full-scale errors for the adc input channels are measured after their respective bias offset errors have been adjusted out. plus and minus full-scale error match this is a measure of how closely the full-scale errors of all chan- nels track each other. the full-scale error match of any channel must be no further away than 10 lsbs from the respective full- scale error of any other channel, regardless of whether the chan- nels are independently sampled or simultaneously sampled.
ad7776/ad7777/ad7778 C10C rev. 0 short circuit current this is defined as the m aximum current which will flow either into or out of the refout pin if this pin is shorted to any potential between 0 v and v cc . this condition can be allowed for up to 10 seconds provided that the power dissipation of the package is not exceeded. signal-to-noise and distortion ratio, s/(n+d) signal-to-noise and distortion ratio, s/(n+d), is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, includ- ing harmonics but excluding dc. the value for s/(n+d) is given in decibels. total harmonic distortion, thd total harmonic distortion is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. for the ad7776/ad7777/ ad7778, total harmonic distortion (thd) is defined as: (v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 ) 1/2 20 log = v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the individual harmonics. intermodulation distortion, imd with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa + nfb, where m, n = 0, 1, 2, 3. intermodulation terms are those for which m or n is not equal to zero. for example, the second order terms include (fa + fb) and (fa C fb) and the third order terms include (2 fa + fb), (2 fa C fb), (fa + 2 fb) and (fa C 2 fb). channel-to-channel isolation channel-to-channel isolation is a measure of the level of cross- talk between channels. it is measured by applying a full-scale 100 khz sine wave signal to any one of the input channels and monitoring the remaining channels. the figure given is the worst case across all channels. digital signal processing applications in digital signal processing (dsp) application areas like voice recognition, echo cancellation and adaptive filtering, the dy- namic characteristics s/(n+d), thd & imd of the adc are critical. the ad7776/ad7777/ad7778 are specified dynami- cally as well as with standard dc specifications. because the track/hold amplifier has a wide bandwidth, an antialiasing filter should be placed on the analog inputs to avoid aliasing of high frequency noise back into the bands of interest. the dynamic performance of the adc is evaluated by applying a sine wave signal of very low distortion to a single analog input which is sampled at a 380.95 khz sampling rate. a fast fourier transform (fft) plot or histogram plot is then generated from which the signal to noise and distortion, harmonic distortion and dynamic differential nonlinearity data can be obtained. similarly, for intermodulation distortion, an input signal con- sisting of two pure sine waves at different frequencies is applied to the ad7776/ad7777/ad7778. figure 11 shows a 2048 point fft plot for a single channel of the ad7778 with an input signal of 99.88 khz. the snr is 58.71 db. it can be seen that most of the harmonics are buried in the noise floor. it should be noted that the harmonics are taken into account when calculating the s/(n+d). 0 ?0 ?0 0 ?0 ?0 ?0 99.88 signal amplitude ?db frequency ?khz input frequency = 99.88 khz sample frequency = 380.95 khz snr = 58.7 db t a = +25 c figure 11. adc fft plot the relationship between s/(n+d) and resolution (n) is ex- pressed by the following equation: s/ ( n + d ) = ( 6.02 n + 1.76 ) db this is for an ideal part with no differential or integral linearity errors. these errors will cause a degradation in s/(n+d). by working backwards from the above equation, it is possible to get a measure of adc performance expressed in effective number of bits (n). s/ ( n+d ) ( db ) C 1.76 n(effective) = 6.02 the effective number of bits plotted vs. frequency for a single channel of the ad7778 is shown in figure 12. the effective number of bits is typically 9.5. 10 7.5 189.2 9 8 8.5 0 9.5 input frequency ?khz effective number of bits sample frequency = 378.4 khz t a = +24 c figure 12. effective number of bits vs. frequency
ad7776/ad7777/ad7778 C11C rev. 0 rtn is tied to refout then the analog input range becomes 0 v to 2 v. the fixed 2 v analog input voltage span of the adc can range from 1 v to 3 v (rtn = 0 v) to 0 v to 2 v (rtn = 2 v), i.e., with proper biasing, an input signal range from 0.3 v to 2.3 v can be covered. both the relative accuracy and differen- tial nonlinearity performance remains essentially unchanged in this mode while the snr and thd performance are typically 2 db to 3 db worse than standard. changing the analog input voltage range by biasing the rtn pin above agnd it is possible to change the analog input voltage range from its v bias v swing format to a more traditional 0 v to v ref range. the new input range can be described as v offset to ( v offset + refin ) where 0 v v offset 1 v. to produce this range the rtn pin must be biased to (refin C 2 v offset ). for instance if outline dimensions dimensions shown in inches and (mm). r-24 24-lead wide-body soic pin 1 0.299 (7.6) 0.291 (7.4) 13 12 1 24 0.419 (10.65) 0.394 (10.00) 0.013 (0.32) 0.009 (0.23) 0.005 (1.27) 0.015 (0.40) 0.614 (15.6) 0.598 (15.2) 0.104 (2.65) 0.093 (2.35) 0.012 (0.3) 0.004 (0.1) 0.019 (0.49) 0.014 (0.35) 0.050 (1.27) bsc r-28 28-lead wide-body soic pin 1 0.299 (7.60) 0.291 (7.39) 15 14 1 28 0.414 (10.52) 0.398 (10.10) 0.03 (0.76) 0.02 (0.51) 0.013 (0.32) 0.009 (0.23) 0.042 (1.067) 0.018 (0.457) 0.708 (18.02) 0.696 (17.67) 0.096 (2.44) 0.089 (2.26) 0.01 (0.254) 0.006 (0.15) 0.019 (0.49) 0.014 (0.35) 0.050 (1.27) bsc 1. lead no. 1 identified by a dot. 2. soic leads will be either tin plated of solder dipped in accordance with mil-m-38510 requirements.
ad7776/ad7777/ad7778 C12C rev. 0 outline dimensions dimensions shown in inches and (mm). c1762C24C1/93 printed in u.s.a. n-28 28-lead plastic dip pin 1 0.550 (13.97) 0.530 (13.462) 1 14 15 28 0.606 (15.39) 0.594 (15.09) 0.012 (0.305) 0.008 (0.203) 0.160 (4.06) 0.140 (3.56) 15 0 0.200 (5.080) max 0.020 (0.508) 0.015 (0.381) seating plane 1.450 (36.83) 1.440 (36.576) 0.105 (2.67) 0.095 (2.41) 0.065 (1.65) 0.045 (1.14) 0.175 (4.45) 0.120 (3.05) s-44 44-pin pqfp 1 44 34 33 23 22 12 11 top view pin 1 0.014 ?0.002 (0.35 ?0.05) 0.031 ?0.002 (0.8 ?0.05) 4 4 0.096 (2.45) max 0.031 ?0.006 (0.8 ?0.15) 0.394 ?0.004 (10 ?0.1) 0.079 + 0.004/?.002 (2 + 0.1/?.05) 0.036 ?0.004 (0.92 ?0.1) 0.036 ?0.004 (0.92 ?0.1) 0.394 ?0.004 sq (10 ?0.1) 0.547 ?0.01 sq (13.9 ?0.25)

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